FPGA and other programmable logic ICs
FPGA is an integrated circuit that contains many (64 to over 10,000)
identical logic cells that can be viewed as standard components.
Each logic cell can independently take on any one of a
limited set of personalities.
The individual cells are interconnected by a matrix of wires and programmable
switches. A user's design is implemented by specifying the simple logic function for
each cell and selectively closing the switches in the interconnect matrix.
Complex designs are created by
combining these basic blocks to create the desired circuit.
Field Programmable means that the FPGA's function is defined by a user's program rather than by the manufacturer of the device.
Depending on the particular device, the program is either 'burned' in
permanently or semi-permanently as part of a board assembly process, or is loaded from an external memory each time the device is powered up.
FPGA links
Information on Field Programmable Gate Array chips and related techniques.
General information
General
- Bringing Parallel Processing to FPGA Designs
- CPLDs readily replace precious µP resources - using CPLDs to offload your CPU lets you create a device that hits an effective performance and cost balance between the conflicting attributes of standard and custom parts
- Detailed model shows FPGAs' true costs - an analysis of all the variables affecting IC development shows that FPGAs are extremely cost-effective at surprisingly high production volumes
- FPGA makes simple FIFO - FPGA-based, synchronous FIFO that uses the same clock for read and write operations
- General Cooking Guidelines for "cooking" up designs with the Spartan-II Family of FPGAs
- Moving beyond programmable logic: if, when, how? - decision to migrate from PLDs and FPGAs to lower cost ASICs seems easy at first glance but may be more complicated than you think, do a little research and analysis before you proceed, and carefully choose which migration path to follow
- Navigating Through FPGA Design - FPGA design process is not as seamless as one might like
- Schmitt Trigger - an idea for cleaning up a noisy clock without resorting to an additional external gate or using an additional internal clock, uses one extra pin and two resistors
- Supply-Voltage Migration, 5V to 3.3V - general notes how it affects FPGA base designs
- The best (or worst?) of both worlds -programmable-logic devices deliver design, manufacturing, and after-sale-service flexibility that ASICs can't match, but CPLDs and FPGAs also run more slowly, burn more power, and cost more per gate, there is emerging one-chip ASIC/programmable-logic hybrid solutions
Arimethics using FPGAs
- A Survey of CORDIC Algorithms for FPGAs - this paper describes the CORDIC algorithm in layman's terms, and discusses implementation issues specific to FPGAs, working copy in pdf format
- Distributed Arithmetic - powerful technique for reducing the size of a parallel hardware multiply-accumulate that is well suited to FPGA designs
- Multiplication in FPGAs - multiplication is basically a shift add operation, but there are variations how to do it, this document is a brief tutorial on multiplication hardware
- The CORDIC Algorithm - class of shift-add algorithms for rotating vectors in a plane
Counters
Signal processing using FPGAs
Digital signal processing has traditionally been done using enhanced microprocessors but recent increases in Field Programmable Gate Array performance and size offer a new hardware acceleration opportunity.
System and design testing and programming
Clock generation and division
Circuit design around FPGA chip
Computer interfacing
Other tips
Hardware description languages are essential tools for handling
the increasing complexity of the hardware designs.
Information on VHDL hardware description language that is used
for designing logic circuits implemented with FPGA or ASIC technologies.
General
VHDL
Verilog
Other languages
- LavaLogic - Java-based synthesis tool
- SpecC
- Superlog - superset of Verilog, borrows features from VHDL and C++
- SystemC - modeling platform that enables, promotes and accelarates system-level co-design and IP exchange
Organizations
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